Semiconductor Engineering

CodaCache Last-Level Cache IP

CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip ...
EDN

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...
Semiconductor Engineering

AI, Performance, Power, Safety Shine Spotlight On Last-Level Cache

Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
EDN

Using OCP and extensions to support system-level cache coherence

Open Core Protocol (OCP) is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
insideHPC

Improving HPC Performance with the Roofline Model

In this special guest feature from Scientific Computing World, Intel’s Cedric Andreolli, Jim Cownie and Kate Antakova explain how the Roofline model can be used to improve HPC code. High performance ...