Business Wire

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMe TM SSD and PCIe® designs using ...
EDN

Who is the EDA leader in SystemVerilog simulation? Part 1

A couple of weeks ago, I took a pre-briefing from the folks at Mentor Graphics and Cadence Design Systems on their plans to standardize on a jointly developed common SystemVerilog verification ...
Design-Reuse

QEMU based Co-simulation platform - Benefits

Semiconductor industry is growing with tremendous pace. Silicon size, features and software complexity have increased to a never before level. Time to market has been reduced and the demand for ...
Yahoo Finance

EVE's ZeBu SystemVerilog Approach Used by Fujitsu Kyusyu Network Technologies to Implement UVM Co-Emulation

SAN JOSE, CA--(Marketwire -09/04/12)- EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have ...