Semiconductor Engineering

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of ...
EDN

Synopsys’ Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction

DPT is a critical technique for ensuring printability of device and interconnect layers in 20-nm IC manufacturing. However, splitting layers into two masks can introduce timing variations as a ...
Nasdaq

Applied Materials Expands Patterning Solutions Portfolio for Angstrom Era Chipmaking

SAN JOSE, Calif., Feb. 26, 2024 (GLOBE NEWSWIRE) -- Today at the SPIE Advanced Lithography + Patterning conference, Applied Materials, Inc. introduced a portfolio of products and solutions designed to ...
EDN

Multi-patterning strategies for navigating the sub-5 nm frontier, part 3

Self-aligned lithographic process techniques are playing an increasingly important role in advanced technology nodes. Even with the growing use of extreme ultraviolet (EUV) lithography, ...