EDN

Cadence and Mentor create free, open-source SystemVerilog methodology

In an effort to make it easier for IC designers to create interoperable SystemVerilog verification flows, Cadence Design Systems and Mentor Graphics today announced that they have jointly created—and ...
EDN

Synopsys, Cadence give nod to SystemVerilog changes

Santa Clara, Calif. – The EDA market's largest suppliers have endorsed the Accellera standards organization's efforts to enhance the SystemVerilog hardware description and verification language, ...
Business Wire

Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation With up to 5X Faster Regressions

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence ® Xcelium ™ Logic Simulator has been enhanced with machine learning technology (ML), called ...