Almost all high-speed SERDES designs require reference clocks that you must properly select to ensure that your links meet jitter requirements of high-speed serial-data communication standards.

With the continued quest for ever-higher performance, the unit interval (UI) for a data valid window continues to shrink. At a 1-Gbit/s rate, the UI is 1000 ps, shrinking to 200 ps at 5 Gbits/s and a ...

Volumes have been written about jitter, an indication of the complexity associated with timing uncertainty. Actually, timing errors are easy to measure. It is in the assignment of blame that the ...

As clock speeds in communications systems push into the GHz range, phase noise and jitter ” always key issues in analog designs ” are becoming increasingly critical to the performance of digital chips ...