Semiconductor Engineering

Multi-Bit In-Memory Computing System for HDC using FeFETs, Achieving SW-Equivalent-Accuracies

A new technical paper titled “Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing” by researchers at University of Notre Dame, Fraunhofer ...
EDN

Numonyx and Intel Achieve Stacked, Cross Point Phase Change Memory Milestone

Numonyx and Intel announced a breakthrough in the research of phase change memory as researchers demonstrated a 64Mb test chip with a thin film technology that enables the ability to stack multiple ...
Semiconductor Engineering

Demonstrating A 2D–0D Hybrid Optical Multi-Level Memory Device Operated By Laser Pulses

A technical paper titled “Probing Optical Multi-Level Memory Effects in Single Core–Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters” was published by researchers at Korea Institute ...
Electronic Design

UMI Scales the Memory Wall in the Chiplet/Multi-Die Era

What are the current challenges involved with incorporating sufficient HBM into multi-die design? How a new interconnect technology can address the performance, size, and power issues that could ...
Computerworld

NetApp boosts entry-level array performance

NetApp on Tuesday announced a major upgrade to its entry-level Fabric Attached Storage (FAS) array that increases performance by as much as three times while also adding six times more memory. The ...