Virtualization of SoC, ECUs and other electronic systems is used to explore (micro-)architectures at system level as well as to develop and verify software early in the design cycle. Key to those ...

MOUNTAIN VIEW, Calif. — Proclaiming a significant step forward for C-language design, Synopsys Inc. will announce on Monday (Feb. 11) a complete SystemC simulation environment. It's already been put ...

CoWare has developed tools for hardware design and simulation centred around the SystemC language. Called ConvergenSC, the software is said to be faster than the reference simulator for SystemC ...

I am amazed how often simulation performance comes up when discussing SystemC and transaction-level modeling. Some of this I can understand. If you are new to transaction-level modeling the ...

Typically, verication is done by synthesising RTL and running it to see how well it performs against the performance specification that were defined at the start of the design. By adjusting the design ...

The concept of system architectural definition at a level of abstraction higher than RTL is a good one. Such methodologies become much more feasible as tools roll out in support. To that end, Synopsys ...

Synopsys has unveiled the DesignWare System Level Library. The library provides high performance SystemC transaction level simulation models (TLMs) for assembling virtual platforms, including ...

Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize ...

SANTA CRUZ, Calif. — You don't need a big corporate CAD budget to get started with SystemC. Summit Design Inc. this week will roll out Vista-PE, a $1,995 “personal edition” of its Vista integrated ...

Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs.