EDN

Book describes writing testbenches using SystemVerilog

SAN FRANCISCO — A book about writing testbenches using SystemVerilog, written by Synopsys Inc.'s Janick Bergeron, has been published by Springer Science + Business Media, the company announced.
Design-Reuse

Synopsys Announces EDA Industry’s First Verification IP Library for SystemVerilog with Methodology Support

MOUNTAIN VIEW, Calif. – March 20, 2006- Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that its VCS® Verification Library, containing DesignWare® ...
Semiconductor Engineering

Shift-Left Low Power Verification With UPF Information Model

Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power ...
Electronic Design

Writing Testbenches Using SystemVerilog

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...