Semiconductor Engineering

LLMs In The High-Level Synthesis Design Flow

A new technical paper titled “Are LLMs Any Good for High-Level Synthesis?” was published by researchers at University of Arizona. Abstract “The increasing complexity and demand for faster, ...
EDN

High-level synthesis package speeds design

The Synphony HLS high-level synthesis package integrates M-language and model-based synthesis and is said to yield up to 10 times higher design and verification productivity than traditional RTL flows ...
Electronic Design

High-Level Design In EDA—Quo Vadis? (Or, Where Are You Going?)

Contributing Editor Frank Schirrmeister examines the historical shifts in the EDA industry, from layout to transistors to gates to RTL, with an eye on what may be next, including electronic-system ...
Semiconductor Engineering

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)

A new technical paper titled “OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs” was published by researchers at Georgia Institute of Technology. “High-Level ...
EDN

Synthesis needs to change to serve modern chip design

As EDA tools evolve, the resulting products try to increase automation. Unfortunately, the last great advance was from schematics to language-based design starting with the first synthesis tools in ...