EDN

After Verilog

EDA vendors are converging on System Verilog as the next step in designing increasingly complex chips, but whether the development language goes far enough to meet the future needs of developers ...
EDN

The battle over Verilog

Warning of possible industry “havoc,” Cadence Design Systems has sounded the alarm about possible incompatibility between System Verilog 3.1 and IEEE 1364 standard Verilog. Cadence's motives are ...
Design-Reuse

nSys Announces the Release of AS nVS, a Verification Solution for Advanced Switching in Verilog

INTEL DEVELOPER FORUM, San Francisco, CA, September 9, 2004 – nSys (Netsys Software Pvt. Ltd.), a rapidly emerging provider of Verification IPs for emerging standards today announced nVS for the ...
Design-Reuse

Verilog register file IP Listing

IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF). It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different ... The ...
Electronics Weekly

VHDL/Verilog training comes with free development board

Esperan is running its project-based HDL training courses through June and July. The aim, says the training company, is to allow designers to implement their project in hardware using supplied ...