EDN

A simpler circuit for characterizing JFETs

Combining Cor Van Rij's JFET test socket with two DMMs, a current limiter, switches and a wall wart yield a simple, accurate ...
IEEE

An Area Optimization Approach for Large-Scale RM-TB Dual Logic Circuits Based on a Multitasking Optimization Algorithm

Abstract: Logic synthesis is a crucial step in integrated circuit design, and area optimization is an indispensable part of this process. However, the area optimization problem for large-scale Fixed ...
Hackaday

LiPo charger

Nothing brings joy to a hacker’s heart like taking a cheap gizmo and making it useful. Over at Hackaday.io [AndyHull] popped open some cheap LiPo battery power packs to see if he could power a Canon ...
IEEE

Leakage Performance of 4H-SiC CMOS Logic Circuits After Gamma Irradiation

Abstract: In this letter, the leakage performances of 4H-SiC CMOS devices, as well as inverter (INV) and NOR logic gate circuits, are evaluated after being exposed to irradiation. It has been observed ...