IEEE

Design and Analysis of a Radix-4 Booth Multiplier with Approximate Computing and Sparsity Adaptation for Convolutional Neural Network Acceleration

Abstract: Efficient hardware multipliers are essential in VLSI systems, especially for compute-intensive tasks such as digital signal processing, image processing, and deep learning accelerators.
IEEE

Performance comparison review of 32-bit multiplier designs

Abstract: This is a study of a relative performance comparison of various 32-bits multiplier designs of Array, Wallace, Dadda, Reduced Area and Radix-4 Booth Encoding multipliers in the Area-Optimized ...