IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...
Scientific Research Publishing

Thach, T.T. (2025) Forecasting Stock Market Indices Using Integration of Encoder, Decoder, and Attention Mechanism. Entropy, 27, Article 82.

ABSTRACT: This project aimed to assess the performance of attention extended LSTM and Gated Recurrent Unit models in stock price movement forecasting. The traditional models suffer from the challenges ...
IEEE

Implementation and Evaluation of a Deep Learning-Based Wireless Decoder Using Real-World Over-the-Air Data

Abstract: Wireless communication forms the backbone of our increasingly connected world. To address the growing demand for faster, more reliable, and adaptive wireless systems, researchers are ...